1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a memory device structure in which a trench capacitor and a MOSFET are connected via a diffusion layer and a manufacturing method thereof. The present invention will be applied to, e.g., a dynamic semiconductor memory (DRAM) and a DRAM/logic-embedded device.
2. Description of the Related Art
With recent development of information communication, the high operating speed and the high integration density of various devices have been required in the semiconductor device technical field. Under the circumstance, an SOC (System On a Chip) technique of integrating circuits having different functions into one chip is rapidly proceeding. Of such devices, a DRAM/logic-embedded device in which a DRAM and logic circuit are integrated into one chip can realize a large-capacity memory and high data transfer speed, and is growing in demand.
FIG. 8 is a sectional view showing an example of a structure of a conventional DRAM/logic-embedded device.
In FIG. 8, a DRAM array region where a buried strap type trench cell is formed, and a logic region where a MOSFET having a salicide structure in a gate/source/drain is formed are formed in a semiconductor substrate 70.
A trench capacitor TC in the DRAM array region includes a deep trench (DT) selectively formed in the semiconductor substrate 70, an impurity diffusion layer 71 (corresponding to a capacitor plate) formed in the deep trench DT, and a doped polysilicon layer 73 (corresponding to a charge accumulation region) buried on the impurity diffusion layer 71 via an oxide film 72 (corresponding to a capacitor insulating film). Part of the oxide film 72 is removed such that the charge accumulation region 73 communicates with a buried strap 74 to be described later on the upper side surface of the trench.
An STI region 75 for isolation is buried in a shallow trench selectively formed adjacent to the trench capacitor TC in the semiconductor substrate 70 so as to cover the upper surface of the charge accumulation region 73 with an insulator.
Each MOSFET gate electrode 76 is formed from a doped polysilicon gate formed on the semiconductor substrate 70 via a gate insulating film 77. The gate electrodes 76 constitute word lines WL commonly connected to the MOSFET gates of cells on the same rows of a cell array.
A thin gate protection insulating film 78 is formed on the side surface of the polysilicon gate electrode 76 by oxidization after formation of the gate electrodes. A thick side wall insulating film 79 is formed from a silicon nitride (SiN) film on the gate protection insulating film 78. A contact barrier film 80 is formed from a plasma silicon nitride (P-SiN) film so as to cover the surface of the side wall insulating film 79.
A drain region 81 and source region 82 of the MOSFET are impurity diffusion regions which are selectively formed in the semiconductor substrate 70 in self-alignment with the gate electrode 76 after formation of the gate protection insulating film. The drain region 81 is shared between two adjacent MOSFETs in the cell array.
A heavily doped impurity diffusion region (contact doping region) 83 with a deep junction is formed at the center of the drain region 81 in self-alignment with the side wall insulating film 79. Metal silicide layers 84 are formed on the upper surfaces of the impurity diffusion region 83 and gate electrode 76.
The buried strap region (BEST) 74 is formed on a side of the trench capacitor TC opposite to the STI region 75 so as to connect the region 74 to the source region 82 and the upper portion of the charge accumulation region 73.
An interlayer dielectric film 85 is formed from a BPSG film so as to cover the semiconductor substrate 70. A cell contact plug (CS) 86 of, e.g., tungsten (W) is buried in a contact hole formed in the interlayer dielectric film 85 at the center of the metal silicide layer 84 in the drain region 81.
A bit line (BL) 87 is formed from a metal wiring layer containing Al as a main component on the interlayer dielectric film 85. The bit line (BL) 87 is connected to the cell contact plug 86.
In the logic region, reference numeral 91 denotes a MOSFET gate electrode; 92, a gate insulating film; 93, a thin gate protection insulating film; 94, a thick side wall insulating film formed from, e.g., a silicon nitride (SiN) film; 95, a contact barrier film formed from a plasma silicon nitride (P-SiN) film; 96 and 97, a MOSFET drain region and source region; 98, a metal silicide layer; 99, a cell contact plug formed from, e.g., tungsten (W); and 100, a metal wiring layer (M1) containing Al as a main component.
As described above, the logic region adopts a salicide structure in which a metal silicide layer is formed on the upper surface of a MOSFET gate electrode/drain region/source region. High performance is realized using a thin film for a MOSFET gate oxide film.
To realize a high integration density and high speed also in the DRAM array region, the MOS polysilicon gate of a cell must be shrunk as much as possible, downsizing the cell. Simple shrinkage degrades the cell performance due to the short channel effect.
In the conventional DRAM/logic-embedded device, when the polysilicon gate of the cell is simply shrunk to realize a high integration degree and high speed in the DRAM array region, the cell performance degrades owing to the short channel effect.